Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network. [electronic resource]

By: Contributor(s): Producer: 20190909Description: 5922-5934 p. digitalISSN:
  • 2162-2388
Subject(s): Online resources: In: IEEE transactions on neural networks and learning systems vol. 29
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Publication Type: Journal Article

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